1. Field of the Invention
The present invention relates to a method for driving a plasma display panel which performs gradation display and, particularly, to a method for driving the plasma display panel using an address while display driving (AWD) scheme.
2. Description of the Prior Art
Plasma display panels having configurations shown in FIGS. 7A to 7C have heretofore been proposed. Each of FIGS. 7A and 7C is a sectional view showing a portion of the plasma display panel for one cell, wherein a transparent front substrate 1, a back substrate 2, partitions 3, a Y electrode 4, an X electrode 5, an address electrode 6, a phosphor 7, and a discharge space 8 are shown.
As shown in FIGS. 7A to 7C, each of the plasma display panels has the structure wherein the front substrate 1 is coupled with the back substrate 2 in an integrated fashion with the partitions 3 being sandwiched therebetween, and the discharge space 8 is defined by the partitions 3 between the front substrate 1 and the back substrate 2. In the plasma display panel having the configuration shown in FIG. 7A, the front substrate 1 is provided with the X electrode 5 and the Y electrode 4 which is parallel with the X electrode 5, and the back substrate 2 is provided with the address electrode 6 which is perpendicular to the display electrodes 4 and 5. The phosphor 7 is placed on surfaces of the, partitions 3 and inside the back substrate 2. In the plasma display panel having the configuration shown in FIG. 7B, the front substrate 1 is provided with the X electrode 5, which is one of a pair of the display electrodes, and the back substrate 2 is provided with the Y electrode 4 which is parallel with the X electrode 5 and which pairs off with the X electrode 5. The back substrate 2 is also provided with the address electrode 6 which is perpendicular to the display electrodes 4 and 5. The phosphor 7 is placed on the surfaces of the partitions 3 each of which is covered with an insulating film (not shown). In the plasma display panel having the configuration shown in FIG. 7C, the back substrate 2 is provided with the X electrode 5 and the Y electrode 4 which are in parallel with each other as well as the address electrode 6 which is perpendicular to the display electrodes 4 and 5. The back substrate 2 is further provided with a partition 9 which is formed between the partitions 3 in such a fashion as to project into the discharge space 8, the partition 9 being integrated with the partitions 3. The X electrode 5 is placed on the back substrate 2 in such a fashion as to face a space defined between one of the partitions 3 and the partition 9, while the Y electrode 4 is placed on the back substrate 2 in such a fashion as to face a space defined between the other partition 3 and the partition 9.
FIG. 8 is a diagram showing wiring patterns of the electrodes 4, 5, and 6, wherein a cell is denoted by 10 and the electrodes which are shown in FIGS. 7A to 7C are denoted by the same reference numerals. Only 4×4 cells are shown in FIG. 8 for brevity, and each of the cells 10 is drawn with the dotted lines.
In FIG. 8, the X electrode 5 and the Y electrode 4 extend along an alignment (hereinafter refereed to as “line”) of the cells 10 in the horizontal (h) direction, and each of the lines is provided with the X electrode 5 and the Y electrode 4. Voltages are applied respectively to the Y electrodes 4 to drive them, but, since the X electrodes 5 are common display electrodes, a voltage is applied to the X electrodes 5 to drive them at a time. The address electrode 6 extends along an alignment of the cells 10 in the vertical (v) direction, and each of the vertical cell alignments is provided with the address electrode 6. Voltages are applied respectively to the address electrodes 6 to drive them.
Referring to the plasma display panels shown in FIGS. 7A to 7C, discharges each having intensity responsive to a specified gradation occur in the cells which are chosen to be lit in each of field periods to thereby cause visible light emissions in the cells at the intensities responsive to the gradation. A choice of a lighting cell or an unlighting cell is performed by applying voltages to the Y electrode 4 and the address electrode 6, thereby forming a wall charge near the Y electrode 4. In the cell where the wall charge is formed so as to produce a forward bias wall voltage, a discharge occurs along a discharge passage indicated by the dotted arrow between the Y electrode 4 and the X electrode 5 due to voltages applied alternately to the Y electrode 4 and X electrode 5. The discharge causes a generation of ultraviolet rays, and the phosphor 7 is excited by the ultraviolet rays to emit the visible light.
Driving schemes for achieving gradation display in plasma display panels include an address display separation driving scheme and an address while display driving scheme. In both of the schemes, the gradation is represented as follows:a0·20+a1·21+a3·23 . . . +an·2n,wherein n is an integer, and ai=0 or 1 (i=0, 1, . . . , n). That is, the gradation is represented by n bit. In the case of 8 bits, for example, 0 to 255 (28=256) gradations are displayed.
In the case of 8-bit gradation display employing the address display separation driving scheme, one field is divided into 8 subfields SF1 to SF8, and each of the subfields SFj (j=1, 2, . . . , 8) is divided into a priming/address period and a sustain period. Lengths of the priming/address period in the subfields SFj are identical to one another, and lengths of the sustain periods of the subfields SFj are in the ascending order of SF1, SF2, . . . , and SF8, i.e., in such a manner as to satisfy a ratio of SF1:SF2:SF3:SF4:SF5:SF6:SF7:SF8 to be:1:2:4:8:16:32:64:128  (1)Here, in each of the sustain periods of the subfields SFj, sustain pulses are supplied alternately to the Y electrode 4 and X electrode 5 (see FIGS. 7A to 7B) on a fixed cycle to thereby generate discharges for light emissions. Accordingly, the number of supplied sustain pulses, i.e., the number of light emissions, and an amount of the light emissions are increased with the increase in the length of the sustain period in subfields SFj as shown in ratio (1). A picture having the 0 to 255 gradations is displayed by properly designating the subfields SFj to emit light.
The priming/address period is a sort of preparation period for performing the light emission. For example, in the plasma display panels having the configurations shown in FIGS. 7A to 7C, wall charges (wall voltages) are formed on the Y electrode 4 and the address electrode 6 in each of the cells by application of a pulse (priming pulse) having a predetermined voltage (a voltage pulse is also applied to the address electrode 6 simultaneously with the application of the voltage pulse to the Y electrode 4 in some cases), and this operation is referred to as “priming”. The priming is performed for each of the cells at a time. After the priming, an address discharge is produced by applying a scan pulse and an address pulse, which are opposite in polarity, to the Y electrode 4 and the address electrode 6 in order to achieve a forward bias, the Y electrode 4 being used also as a scan electrode and the address electrode 6 extending on a cell to be lit. Owing to the thus-produced address discharge, a wall charge to be formed on the Y electrode 4 of the cell to be lit has a polarity required for sustaining the discharge in the lighting cell. This is an addressing for choosing the lighting cell. When choosing an unlighting cell, the choice is made in the same manner as in the choice of lighting cell although a required polarity is different from that of the lighting cell.
In the plasma display panel having the configuration shown in FIG. 7A, each of the partitions 3 is formed from a dielectric, and a negative glow discharge is used as a discharge scheme in the case of a short gap length. Such plasma display panel has a problem that the dielectric of the partition 3 inhibits the formation of a positive column generated by the glow plug if the gap length is lengthened. The plasma display panel having the configuration shown in FIG. 7B wherein each of the partitions 3 is a metal partition (Japanese Patent Laid-open No. 11-312470) and a plasma display panel having the configuration shown in FIG. 7C (Japanese Patent Laid-open No. 2000-306516) have been proposed in order to solve the above problem. In each of the plasma display panels of FIGS. 7B and 7C, since the discharge passage indicated by the dotted arrow is satisfactorily long as compared with the plasma display panel of FIG. 7A, an efficient positive column is formed and a coating area of the phosphor is enlarged to increase the amount of light emission, thereby realizing a high degree of emission efficiency. Further, there have been proposed a plasma display panel which is improved in the emission efficiency and realizes a high degree of brightness by producing narrow pulse discharges between the display electrode 4 and the metal partition 3 and between the display electrode 5 and the metal partition 3 in place of using the positive column mode of the glow discharge.
In the above-described plasma display panels, intensity of light emission is increased with an increase in the sustain period which contributes to the light emission. A proportion of the sustain period to one field period is usually referred to as “duty ratio of light emission”, and the duty ratio of light emission of the above plasma display panels employing the address display separation driving scheme is the following value (Shigeo Mikoshiba and Heiju Uchiike “All about Plasma Display” Kogyou Chousakai Publishing Co., Ltd. pp. 154–155.
More specifically, the time required as an address period for obtaining a sufficient wall charge is about 3 μsec. The priming is performed for all the cells at a time; however, the addressing is performed for each of the lines sequentially and, therefore, the time required for addressing all the lines if the number of lines in a plasma display panel is 480, for example, is:480×3 μsec=1.44 msec.This is the time length of the address period in one subfield. In the case of 8-bit 256-gradation display, the total time length of address periods in one field becomes 11.52 msec because each of the fields consists of 8 subfields. Accordingly, in view of the time length of one field of 16.7 msec, the time length of sustain period in one field is:16.7 msec−11.52 msec=5.18 msec,and this means that a proportion of the sustain period to the time length of one field, i.e. the duty ratio of light emission, is as small as 31%.
Further, the inventors of the present invention have conducted an experimental manufacture of a plasma display panel wherein the metal partitions were used as the partitions 3 (see FIGS. 7B to 7C), and the above-described narrow pulse discharge was performed using the plasma display panel. The experiment has revealed a problem that a space charge is increased cumulatively in the discharge space 8 (see FIGS. 7B to 7C) due to the narrow pulse discharge to deteriorate intensity of an electric field which is formed between the display electrodes 4 and 5, thereby impeding improvement in the emission efficiency. It has also been found that lengthening of a cycle of repeating sustain discharges in a sustain period and reduction of the space charge by sufficient neutralization are effective for the prevention of the problem; however, the lengthening of the cycle requires a reduction in the number of sustain discharges in the sustain period, which causes deteriorations in the duty ratio of light emission and the brightness. Thus, it has been confirmed that the lengthening of the repeating cycle of the sustain discharges in the address display separation driving scheme is considerably difficult from the practical standpoint.
As compared with the address display separation driving scheme (ADS), it is possible to maintain a duty ratio of light emission of 90% or more in the address while display driving scheme (AWD). Therefore, it is possible to lengthen the cycle of repeating sustain discharges in the sustain period. The AWD will be described below based on the above-mentioned literature “All About Prism Display”.
In the case of 3-bit 8-gradation display, one field is divided into 3 subfields, and a first H period of each of the subfields (H means a scan period for one line, i.e., one horizontal scan period (=63.5 μsec)) is used as the priming period. Here, a ratio among the subfield SF1 of the bit 1, the subfield SF2 of the bit 2, and the subfield SF3 of the bit 3 should be 1:2:4 in view of ratio (1), a length of the subfield SF1 is:262.5H÷(1+2+7)=37H with the remainder of 3.5H  (2).Thus, a length of the subfield SF2 is set to 74H (37H×2), and a length of the subfield SF3 is set to 148H (37H×4). In addition, if the following equation is satisfied,262.5H−(37H+74H+148H)=3.5Hand the subfields SF1 to SF3 are each set as described above, the remainder of 3.5H; however, this is ignored because it is only 1.3% of one field.
Shown in FIG. 10 are driving timings for achieving the 3-bit 8-gradation display, wherein a time axis (lower one), which uses the line 1 as the reference line and an H period as the unit, and subfield periods (upper one) are used to enter the horizontal axis, while lines from the line L1 to the line L240 are used to enter the vertical axis.
In FIG. 10, a subfield SF1 of the line L1 consists of 37H (0H to 36H), and the first period, which is 0H, is set to be an address period A. A subfield SF2 consists of 74H (37H to 110H), and the first period 37H is used as the address period. A subfield SF3 consists of 148H (111H to 258H), and the first period 111H is used as the address period. Timings in the line L2 are such that the timings for the subfields SF1 to SF3 of the line L1 are respectively delayed by one H period, and timings in the line L3 are such that the timings for the line L2 are respectively delayed by one H period. That is, the timings are respectively delayed by one H period and, therefore, the address periods are respectively shifted by one H period with the increase in the line number.
An address period B of the subfield SF2 of the line L1 falls on 37H, and an address period C of the subfield SF1 of the line L38 falls on the same period 37H. In the succeeding lines, up to line L240, an address period D of a subfield SF3 of a line L112 of a preceding field falls on the same period. This means that the address periods B, C, and D of three lines are overlapped in one period. Such phenomenon occurs repeatedly with the lapse of time.
However, the addressing cannot be performed for a plurality of lines at a time. Therefore, one H period, which is used as one address period in the above example, is divided into three periods of a first region, a second region, and a third region as shown in FIG. 11, and, in each of the lines, the first region is used as an address period of a subfield SF1 of a bit 1, the second region is used as an address period of a subfield SF2 of a bit 2, and the third region is used as an address period of a subfield SF3 of a bit 3. In FIG. 10, for example, a first region of 37H is used as an address period of the subfield SF1 of the line 38, a second region of 37H is used as an address period of the subfield SF2 of the line L1, and a third region of 37H is used as an address period of the subfield SF3 of the line L112. Thus, even if it is necessary to perform the priming/addressing operations for a plurality of lines in one H period, it is possible to vary the timings for them.
Further, according to the above driving scheme, it is possible to use the period (2H/3) other than the address period in the first H period in each of the subfields of each of the lines as a sustain period.
The foregoing is a description of the address period, and, in general, a reset period for removing a wall charge from the Y electrode 4 (see FIGS. 7A to 7C) in each of the cells as well as a priming period for forming a wall charge having a predetermined polarity on the Y electrode 4 (in some cases, a wall charge may be formed also on the address electrode 6 at the same time) are usually precedent to the address period. The Y electrodes 4 for the respective lines are independently driven, and one H period precedent to the H period which is used as the address period or an aH period (a≧2) having a time length of aH (a is a positive integer) is used as the reset period and the priming period. Further, the reset and the priming may sometimes be performed in the address period or an H/3 period.
The foregoing is a description of the 3-bit 8-gradation display. In the case of the 8-bit 256-gradation display, 8 subfields in the ratio represented by ratio (1) are set for each of fields. A first H period in each of the subfields is divided into 8 regions. An address period is set in one of the regions of each of the subfields with a delay of one region per subfield in such a manner that the first region of the subfield SF1 is used as the address period and the eighth region of the subfield SF8 is used as the address period. Also in this case, it is possible to use a period (7H/8 period) other than the address period in the first H period as the sustain period. Further, one H period preceding the H period which is used as the address period is used for performing the reset and the priming in this case; however, a period having a time length of aH (a is integer and 2 or more) is used for forming a sufficient wall charge from a space charge formed after the reset. If the reset period and the priming period can be shortened, the reset and the priming may sometimes be performed in H/8 period of the address period.
According to the above driving method, the sustain period is a period having a time length obtained by subtracting the reset period and the priming period of the first H period of each of the subfields, the address period of H/3 period subsequent to the fist H period, and the remainder period of 3.5H from one field period. In the case of the 3-bit 8-gradation display, a total of the periods other than the sustain periods is approximately:(1H+H/3)×3+3.5=7.5H,which means that the duty ratio of light emission is about 97%.
Since it is possible to increase the duty ratio of light emission as described above, the repeating cycle of the sustain discharges in the sustain period can be increased. As shown in FIG. 11, which is an example of the increased repeating cycle in the case of the 3-bit 8-gradation display, the repeating cycle is TH/3 (TH is a cycle of horizontal scan periods). In the case of the 8 bit 256-gradation display, it is possible to set the repeating cycle to TH/8. That is to say, it is possible to set the repeating cycle to TH/n in the case of n-bit gradation display. Further, in accordance with the relationship between the address periods and the sustain periods, it is possible to set a time length of the repeating cycle to be aTH/n (a is a positive integer) or (TH/n)/a (a is a positive integer). Thus, the repeating cycle has a considerably high degree of freedom while it may be discrete.
As described above, although the address while display driving scheme realizes the improvement in the duty ratio of light emission, the lengthened repeating cycle of sustain discharges in a sustain period even in high-gradation display, and the prevention of cumulative increase of space charges which are generated when employing the narrow pulse discharge method, 2H periods cannot be used as the sustain period in each of the subfields when the scheme is employed because one H period is used for each of the reset/priming and the addressing in each of the subfields in the scheme. If the time required for each of the reset/priming and the addressing is shortened, it is possible to lengthen the sustain period and to further increase the duty ratio of light emission, thereby further improving the emission efficiency.